1. Field of the Invention
The present invention relates to a method for forming a semiconductor device, in particular, a method for forming a semiconductor device in which a source and drain diffusion layer for a plurality of memory cell transistors is connected with a buried bit line.
2. Description of the Related Art
A method for forming a bit line connecting a plurality of memory transistors of a semiconductor device, as a diffusion layer formed in a semiconductor substrate, has been conventionally developed.
An example of a device manufactured by the conventional method is shown in FIG. 9 and FIG. 10. In the device, an active region 22 is formed in a desired shape on a semiconductor substrate 21, and a gate electrode 23 is formed so as to cross at a right angle with respect to the active region 22. A bit line 24 is formed parallel to the gate electrode 23 by a diffusion layer to connect each transistor formed on the active region 22. A device isolation film 25 is formed in the region where the active region 22 and the bit line 24 are not formed and a thin oxide film 29 is formed over the bit line in the active region.
In case of forming a memory cell having a structure described above, a thick insulating film is formed on the semiconductor substrate 21 as the device isolation film 25 to define the active region 22 and a bit line 24 formation region. Subsequently, the gate electrode 23 is formed. A bit line 24 and source/drain region are formed by implanting ions simultaneously by using the gate electrode 23 and the device isolation film 25 as a mask.
However, as seen from FIG. 11, there is a possibility that the gate electrode 23 may not be correctly aligned with the bit line 24 formation region, overlapping the bit line 24 formation region. If the overlapping occurs, as shown in FIG. 12, the channel region under the gate electrode 23 is in contact with the bit line 24 formation region in the region 100 so as to connect each of the transistors aligned in a bit line. To avoid overlapping, a margin Y of the alignment (see FIGS. 9 and 10) is required between the gate electrode 23 and the bit line 24 formation region. However, retaining the margin Y of alignment causes an increase in cell area. Therefore, there is a drawback that the cell can not be miniaturized, while avoiding the overlapping.
Alternatively, another method is known in which a thick insulating film is formed on a bit line formation region as a device isolation film.
In this method, as shown in FIG. 13 and FIG. 14, a resist is formed by photolithography method in the region other than a buried diffusion layer 34 formation region, and a buried diffusion layer 34 is formed as a bit line by implanting ions using the resist as a mask. After removing the resist, an oxide film and anti-oxide film are formed and the anti-oxide film is removed except for the region on the active region 32. Then, the oxide film is oxidized, thereby forming a device isolation film 35 in the region except for the active region 32 which includes a thin oxide film 39 as shown in FIGS. 15 and 16. Subsequently, a gate electrode 33 is formed on the active region 32 and the device isolation film 35 positioned as generally indicated in FIGS. 13 and 14. Source/drain is formed by implanting ions using the gate electrode 33 as a mask.
According to the method, as shown in FIG. 15, which is a sectional view along line B--B' of FIG. 13, since the resist used as a mask for the buried diffusion layer and the anti-oxide film for forming the device isolation film 35 are formed separately, the buried diffusion layer 34 may extend beyond from under the device isolation film 35 to the active region 32 when the resist and the device isolation region are not aligned correctly. If the gate electrode 33 overlaps thereon as shown in FIG. 16, which is a sectional view along line C--C' of FIG. 13, the buried diffusion layer 34 is formed in the channel region under the gate electrode 33. As a result, the characteristics of transistor may be adversely affected and there is a fear that the buried diffusion layer 34 is connected with both of the source and drain diffusion layer 41 in a transistor. Therefore, minimization of a device can not be achieved with a high quality by this method.